1. Field of the Invention
The present invention relates generally to Liquid Crystal Device (LCD) video displays and more particularly to the use of redundant, integrated select line driver circuitry in the fabrication of a scanned active matrix (AM) LCD.
2. Description of the Prior Art
LCD displays offer benefits which are not achievable in conventional cathode ray tube displays. LCD thinness, low weight, low power consumption and ruggedness are advantageous for a variety of applications, ranging from portable personal computers to avionics displays.
LCD displays which use twisted nematic liquid crystal material are well known. In display systems of this type, the liquid crystal molecules align themselves in the absence of an electrical field in such a manner as to twist polarized light to pass through an exit polarizer. In the presence of an electric field, the crystals align themselves so that polarized light is not twisted and will be blocked by the exit polarizer. Thus, for a back-lighted LCD display, a viewer sees a lighted pixel in the absence of an electric field and a dark pixel in the presence of an electric field.
Individual pixels in some LCD displays are activated using active matrix (AM) technology. In AM LCD display devices, an active device (for example, a thin film transistor or TFT) is present at each pixel site. In a scanned AM LCD display, the gate contacts of the transistors are attached to select lines (also known as gate lines), the source contacts of the transistors are connected to data lines, and the drain contact of each transistor is connected to one plate of capacitor formed by a liquid crystal dielectric layer sandwiched between two electrodes, at least one of which is transparent. The AM matrix display is scanned one row (line) at a time by applying a select voltage value to the select line associated with that row. In response to the select voltage, the TFT's in the row are conditioned to charge their respective capacitors to the potential values supplied by the respective data lines. These charge values change the electric field applied to the LC material and, so, lighten or darken the individual pixel cells in the row. When all of the rows of the matrix have been scanned, an image is formed on the LCD matrix.
In integral scanned AM LCD arrays, the scanning and data logic are formed directly on the substrate on which the individual pixel capacitors and TFT's are formed. The data logic may include, for example, a shift register and a parallel data register to hold the data values for one line of the display. The select logic may include a shift register for propagating the select signal from the top line position of the display to the bottom line position in one frame interval.
An underlying problem in the development of large AM LCD panels is the difficulty of reliably addressing a single pixel through this data and select logic and through the relatively large electronic grid of data and select lines. In contrast to a CRT, in which a pixel may be addressed simply by directing an electron beam electrically and magnetically to a desired spot, the LCD display includes the data and select logic as well as a pair of conductive paths for each pixel.
As the panel size increase, the complexity of the data and scanning logic and of the conductive paths increases. Furthermore, as pixel density increases, smaller components in the data and scanning logic and thinner conductive paths become more desirable. These two effects make the reliability of the data and scanning logic and of the conductive paths an important issue in the fabrication of an LCD display.
U.S. Pat. No. 4,804,953 to Castleberry discusses a method for providing redundancy in the data and gate lines between the LCD cells. The data lines and the gate lines are formed during each of two metalization steps to provide the desired redundancy. The first conductive data line layer is fabricated in the same process stage as the silicon gate electrodes of the TFT switching elements. An insulating layer is fabricated in the same process stage as the gate insulating material. The second conductive layer for the data lines is fabricated in the same process stage as the source and drain metalizations. The two conductive layers are in contact along approximately 90 percent of the length of each data line.
U.S. Pat. No. 4,368,523 to Kawate discusses an LCD device fabricated with redundant pairs of data and select lines. In this configuration, each cell of the LCD display includes four TFT switches, one for each possible combination of data and select lines. Any of these four switches may control the cell. When a defective TFT, data line or select line is detected during testing, it may be cut away using a laser, leaving the other three TFT's, the other data line and/or the other select line active. Thus, this apparatus may recover from multiple failures in the data or select lines and in the TFT switches.
As the reliability of the electronic grid of select and data lines increases, other failure mechanisms become dominant in limiting the yield of AM LCDs. For externally scanned LCD's a failure in the numerous connections between the display device and the external data and scanning logic is one of these failure mechanisms. When the row and column drivers are external to the display matrix, the driver to matrix connections can limit the system reliability. The problem increases as the size of the panel (and the number of driver-to-matrix interconnections) grows larger.
When the select line and data line driver circuits are integrated onto the glass substrate, along with the AM display (i.e. an integral scanned AM display), the number of external connections may be reduced by 70 percent or more, depending on the display size. This type of display may be more reliable, more compact and have a reduced power consumption compared to an externally scanned matrix. The elimination of most of these external connections provides enough room on the substrate to make the remaining leads larger and, therefore, more reliable. This area is also available for implementing the data and scanning logic circuitry.
The Kawate patent also discusses an embodiment in which the data and select logic of an LCD display are integrated onto the same substrate as the display, and are implemented redundantly. The primary and redundant select logic are placed, respectively, at the left and right sides of the display, and the primary and redundant data logic are located respectively at the top and bottom of the display. If the shift register in the select logic on one side of the matrix has a defective stage, then the shift register on the opposite side of the device may be used instead. If, however, both select logic shift registers have defective stages then the portion of the display below the lower-most defective stage cannot be used since there is no way to apply a select pulse to the TFT's in those rows of the matrix.